This invention relates to a wiring structure for a semiconductor element, more particularly to a wiring structure used for forming an electric circuit such as an integrated circuit on a semiconductor chip, and the invention further relates to a method for forming such a wiring structure.
FIG. 15 illustrates an example of a semiconductor chip 101 including an exemplary wiring structure which is formed by way of a prior art wiring method. As shown in the figure, the semiconductor chip 101 includes an electrode ER which is led from the circuit formed on the chip (for simplification, referred to as `circuit electrode ER` hereinafter), which is formed inside the circuit formation area 102 according to a predetermined process. The chip 101 also includes a bonding pad BP for wire bonding which is formed in the peripheral area of the circuit formation area 102. This bonding pad BP act as a junction point which electrically connects the internal chip circuit with an external circuit.
In the semiconductor chip 101 described in the above, the circuit electrode ER and the bonding pad BP have been generally connected with each other through a wiring pattern 105 which is formed within the circuit formation area 102, or through a wiring pattern 106 formed outside the same.